Improvements in and relating to Data Comparison

The patent is the representation of a low cost TTL circuit developed to recognise a binary input pattern as a percentage of that input which as application-specific integrated circuit (ASIC) logic will enable on chip CCD cameras to focus and recognise objects at the speed of the CCD rather than the bus between the CCD and processor adding delays. The ASIC logic also has the ability to recognise degraded digital sine waves patterns as true and reconstruct signals in a bridge, text and objects using logical masks.

Patent Application will time out on 30 April 2014 unless a buyer is found.

Attached files:











Patents:
EP 121,655,906 issued 2012-05-25   [MORE INFO]

Type of Offer: Sale

Asking Price: US$50,000



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