Dynamic reconfigurable memory hierarchy

A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.

Patents:
US 42,213

Inventor(s): DWARKADAS SANDHYA [US]; BALASUBRAMONIAN RAJEEV [US]; BUYUKTOSUNOGLU ALPER [US]; ALBONESI DAVID H [US]

Type of Offer: Licensing



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