TRIPS: a Third-Generation Computer Architecture
Background Conventional CPU architectures are hitting hard limits in the following areas: operating frequency, efficiency, and power consumption. The historical 55% annual increase in CPU performance is likely to drop to 20%. In addition, computer applications are becoming more diverse: many types of specialized solutions have emerged and many applications have varying phase behaviors.The TRIPS project has developed technology scalable processor and memory system technologies for nanoscale microprocessor chips. These technologies are intended to mitigate increasing on-chip communication latency, to provide power efficiency and reduce design complexity for high-performance systems, and to provide programmers with familiar instruction execution models.
Invention Description TRIPS (Tera-op, Reliable, Intelligently adaptive Processing System) is a revolutionary new microprocessor architecture being built in the Department of Computer Sciences at The University of Texas at Austin. This new scalable computer architecture has a dramatic increase in parallel instruction execution (approximately 3X to 10X increase) and is fundamentally aligned with future technology characteristics. It also allows for dynamic resource configuration (polymorphism), in which it structures the machine resources, then runs the program, allowing the same hardware to run broader sets of workloads better. The team’s goal is to produce a scalable architecture that can accelerate industrial, consumer, embedded, and scientific workloads, reaching trillions of calculations per second on a single chip
The TRIPS team is currently bringing-up first-silicon in the lab, and is developing the software needed to evaluate this new class of architectures on embedded, streaming, scientific, and desktop workloads.
Benefits
Significantly more powerful uniprocessors Powerful uniprocessors lead to better multiprocessors Polymorphism leads to better performance on broader range of workloads Appropriate leverage for expensive future technologies
Features
Takes advantage of multiple computation nodes Explicit Data Graph Execution (EDGE) instruction set architecture Scalable and distributed processor core composed of replicated heterogeneous tiles Non-uniform cache architecture and implementation On-chip networks for operands and data traffic Configurable on-chip memory system with capability to shift storage between cache and physical memory Composable processors constructed by aggregating homogeneous processor tiles Compiler algorithms and an implementation that create atomically executable blocks of code Spatial instruction scheduling algorithms and implementation
Market Potential/Applications Conventional processor markets: Machine vision and image processing (streaming)
Cell phone base stations (signal processing)
Game consoles (embedded supercomputing)
Enablement of emerging technologies BioTech workstation for example: Protein folding, docking and scoring - Deskside BlueGene NanoTech workstation: Molecular-level modeling, simulation & analysis Virtual SE The current application suite includes desktop/workstation applications (SPEC), embedded applications (EEMBC), and signal processing applications.
Development Stage Proof of concept
IP Status Two U.S. patent application filed
UT Researcher Douglas C. Burger, Ph.D., Computer Sciences, The University of Texas at Austin Stephen W. Keckler, Ph.D., Computer Sciences, The University of Texas at Austin Karthikeyan Sankaralingam, Computer Sciences, The University of Texas at Austin Ramadass Nagarajan, M.S., Computer Sciences, The University of Texas at Austin
Type of Offer: Licensing
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