System and Method for Testing High-Speed VLSI Devices using slower Testers

BACKGROUND: The operating speed of VLSI circuits is constantly increasing and even small delay faults can cause these circuits to malfunction. Delay testing, which applies pre-generated test vectors to the circuit during its intended operating speed, can ensure the circuit's temporal correctness. However, current testers are usually several times slower than the speed of the new VLSI designs. This gap between the speeds of the testers and the high-performance designs is likely to continue into the forseeable future, which calls for the development of methods to test fast VLSI designs on slower testers.

DESCRIPTION: Scientists have developed a novel method for generating vectors that can be used in a slow tester for testing high-speed VLSI devices and circuits.

APPLICATIONS: This new invention has applications in testing high-speed VLSI circuits, particularly where the tester speed is considerably lower than the circuit speed.

ADVANTAGES: The new technology provides the key benefit of enabling current testers to test circuits having speeds much higher than their own.

This technology available for licensing on a non-exclusive basis.

REFERENCE: 1999-298

Patents:
US 6,345,373   [MORE INFO]

Type of Offer: Licensing



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