New Method for Concurrent Error Detection and Correcting

BACKGROUND: The spread of technology into hostile environments has increased the need for dependable machine execution without compromising performance levels. The de facto model used for describing fault tolerant systems is the single-event upset (SEU) model, which specifies a maximum of one error per cycle. While SEU compliant machines should be able to operate under constant error rates of one fault per cycle, many do not due to prohibitive overhead, and thus many machines are often only partially SEU tolerant. In general, existing error detection and correcting (EDC) solutions suffer from high cost and fail to provide adequate levels of resilience. Triple modular redundancy (TMR) is the leading technique currently used, however, its large overhead forces many systems to implement only partial TMR, resulting in inadequate SEU tolerance. Real-world applications require EDC techniques capable of providing tolerance with constant error rates far in excess of the SEU model. In order to be effective, these methods must provide elevated levels of resilience with relatively small overhead, without compromising machine performance.

DESCRIPTION: Researchers at the University of California have developed a novel EDC technique that allows for the construction of machines that are completely resilient to single bit errors with little overhead in terms of both added redundancy and logic complexity. The new method can be expanded to provide coverage for many kinds of multiple error conditions, and there is potential that this technology will allow construction of machines capable of correct behavior even under constant error rates well in excess of one error per cycle. The newly discovered method for adding redundancy is at minimum six (6) times more efficient than TMR. Additionally, this new technique can decrease encoder/decoder delay by 30%-50% as compared to current optimized Hamming Codes at minimal cost.

ADVANTAGES: This novel fault tolerance technique is vastly superior to existing EDC solutions, which suffer from high cost and fail to provide adequate levels of resilience. The invention has the following important advantages:

* Increased machine performance at lower costs as compared to current EDC techniques;
* Design-specific method is capable of meeting design constraints in many applications;
* Selectable performance and area cost trade-offs;
* Reduction in circuit area, delay and power required for EDC.

APPLICATIONS: Real-world applications of this discovery include:

* Machine operation in hostile environments, such as deep space and locations with high levels of radiation, where dependable execution is critical;
* On-chip memory compilers.

PUBLICATIONS:

* "Fault Tolerant Finite State Control Using Low Density Parity Checking" G. Hoover, F. Brewer.

This technology is available for licensing. Patent Pending. PATENT STATUS: US Publication No. 20080059869 published March 6, 2008
REFERENCE: 2005-752

Type of Offer: Licensing



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