Problem Solver

Rajthilak S

Rajthilak S

Areas Rajthilak S is Knowledgeable in:

Digital System Design and Analog Circuit Design.

Techniques Rajthilak S Uses:

For Digital System Design, I use Xilinx Vivado tool to design my specification using HDL (Hardware Description Language). The designed product is verified using HVL (Hardware Verification Language or methodology) and the designed product design is synthesised to hardware components. It is followed by floor planning , place and routing. I perform the entire design flow of VLSI Design. I use Design Compiler to estimate the area, power and Performance of the design.
For Analog Circuit Design,i take a particular block of the design and I use Hspice to Model the circuits in transistor level and verifiy its working and I have the knowledge of Verilog-A to model the transistors.

Rajthilak S's Problem Solving Skills:

  1. Design Methodologies and flow
  2. Analog Logic Design
  3. Digital System Design
  4. Hardware Description Languages (Verilog)
  5. Hardware Verification Languages (System Verilog and UVM)
  6. Power , Performance and Area estimation

Rajthilak S's Problem Solving Experience:

  1. I have designed and verified AMBA's APB (Advanced Peripherial Bus) architecture. I was designed using Verilog and Verified using System Verilog and UVM.