Adaptive clocking system for a packet classifier

An adaptive clocking system 100 for a packet classifier is described. The system provides for control of the clocking frequency of the packet classifier dependent on the traffic within the packet based network. By operating the packet classifier at a frequency commensurate with the traffic encountered it is possible to match fluctuations in the traffic and effect power savings during periods of low traffic. The system comprises a buffer 120 for storing the packet header information of received packets 160 and a comparator 130 for determining the number of buffer slots occupied by the information. A controller selects one of a plurality of different clocking frequencies for clocking the packet classifier dependent upon the number of occupied buffer slots. The packet classifier may divide a ruleset into multiple groups, each containing rules that can be processed in a linear search and SRAM with a long word line may be used so as to reduce the number of clock cycles required to perform the linear search on selected rules.

Attached files:
GB 2463889.jpg

Patents:
GB 2,463,889

Inventor(s): KENNEDY ALAN [IE]; WANG XIAOJUN [IE]; ZHEN LIU [IE]

Type of Offer: Sale



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