Ram Memory Element with One Transistor

The invention relates to a memory element consisting of an MOS transistor having a drain (8), a source (7) and a body region covered by an insulated gate (12), wherein the thickness of the body region is divided into two distinct regions (13, 14) separated by a portion of an insulating layer (16) extending parallel to the plane of the gate.

Attached files:
WO 2010119224.jpg

Patents:
WO 2,010,119,224

Inventor(s): CRISTOLOVEANU SORIN IOAN [FR]; RODRIGUEZ NOEL [ES]; GAMIZ FRANCISCO [ES]

Type of Offer: Sale



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