Method for parameterized model order reduction of integrated circuit interconnects
The present invention is a method and apparatus for creating a reduced-order IC interconnect model, which incorporates variations in interconnect process parameters, and models both on-chip and off-chip interconnects. The method is based on mathematically representing an IC interconnect system, including mathematical interconnect process parameter terms, which are manipulated to facilitate simplification of an IC interconnect model. The IC interconnect model is then simplified by using a mathematical technique called state-space projection. Specifically, an IC interconnect system is represented with at least one modified nodal analysis equation (MNA) that is based on frequency, interconnect process parameters are added and substituted back into the MNA(s), terms with interconnect process parameters are explicitly matched. A state-space projection is created, which implicitly matches frequency terms. The state-space projection is used to create the reduced-order IC interconnect model.
LI XIN [US]; LI PENG [US]; PILEGGI LAWRENCE T [US]
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