System and Method for Efficient and Optimal Minimum Area Retiming

A method for use in electronic design software efficiently and optimally produces minimized or reduced register flip flop area or number of registers/flip flops in a VLSI circuit design without changing circuit timing or functionality. The method dynamically generates constraints; maintains the generated constraints as a regular tree; and incrementally relocates registers/flip flops and/or the number of registers/flip flops in the circuit design.

Attached files:
WO 2009097601.jpg

Patents:
WO 2,009,097,601

Inventor(s): ZHOU HAI [US]; WANG JIA [US]

Type of Offer: Licensing



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