Asymmetric Clustered Processor Architecture based on Value Content

Background: Most conventional clustered processor architectures are symmetric systems. It is known that the scalability of ahigh-performance processor architecture has been limited in new system designs by various factors, including increasing clock frequencies, issue widths, and greater wire delays. In addition, many high-performance processor families have extended their Instruction Set Architecture (ISA), or have introduced new ones, to handle 64 bit integers, which further exacerbates the above design factors. Clustered processors have been proposed and implemented (Digital Alpha21264) to cope with wire-limited designs. Clusters have always been identical. This prevented increased execution speed even though the majority of instructions could be executed faster because of their narrow operands. To use a faster cluster required a new datapath design and a way to determine when it can be used Technology: University researchers have developed a method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture. The asymmetric clustered processor apparatus includes a narrow cluster, a wide cluster, a steering logic utilizing a cluster predictor for providing a decoded instruction to either the narrow cluster or the wide cluster; address registers which are not part of the ISA, and a translation look-aside buffer for translating the virtual address of a load/store instruction in parallel with an execute stage. The method includes the steps of: predictably steering the instruction to either a W bit Wide integer cluster or an N bit Narrow integer cluster, managing the Address register file, and processing any instruction in the Wide integer cluster but processing only N bit instructions in the Narrow integer cluster. Application: This invention can be used for designing better processors, for faster speed and/or low power consumption and/or reduced wiring complexity and/or reduced hardware complexity.

Patents:
US 7,380,105

Type of Offer: Licensing



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