Fastlock Integer/Fractional-N Hybrid PLL Frequency Synthesizer

Summary Settling time is an important performance metric in the phase-locked loop (PLL) frequency synthesizers. To achieve a fast settling time, the PLL loop bandwidth should be increased. In the widely used charge pump PLLs, however, the loop bandwidth cannot be undoubtedly large, but rather, is limited to about 10% of the reference frequency to maintain the loop stability. Due to the 10% bandwidth rule, for a given frequency resolution, fractional-N PLLs have a faster settling time than integer-N PLLs. This is because the former has a higher reference frequency than the latter. The faster settling of the fractional-N PLL, however, comes at a price of increased hardware complexity and power dissipation, since the fractional-N frequency synthesis necessitates the use of phase interpolators or high-order modulators to suppress the steady-state fractional spurs. The invention is a new architecture of a fastlock PLL frequency synthesizer. The architecture has the wide loop bandwidth of the fractional-N PLL in the tracking state and the narrow loop bandwidth of the integer-N PLL in the locked state. The proposed architecture can have fast settling time of the fractional-N PLL, while maintaining the same hardware complexity as the integer-N PLL. The hybrid PLL architecture is essentially an integer-N PLL which is faster than the normal integer-N PLL.

Patent Status: Pending

Applications Wireless base stations; mobile hand sets; personal digital assistants (PDAs), broadband wireless access; satellite communications; local area networks (LANs). For Further Information Please Contact the Director of Business Development Daniel Behr Email: daniel_behr@harvard.edu Telephone: (617) 495-3067

Inventor(s): Ham, Donhee

Type of Offer: Licensing



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