Error Correcting Sigma-Delta Modulation Decoding

Summary Conventional sigma-delta analog-to-digital conversion (ADC) systems may be significantly enhanced by using a recently developed novel design approach. The technique involves instrumenting an ADC’s modulator subsystem with an observation circuit to provide quantized estimates of the modulator’s state values. This observation circuit provides a limited precision estimate of the modulator state values (delay stages), but leaves the modulator’s input/output relationship unchanged. A separate processing function is performed on these state estimates—which are filtered separately—and the result is added to the output of the decimator subsystem. A closer approximation to the input value than would otherwise be available is thus achieved.

Applications Conventional ADCs (such as dual slope, successive approximation, and flash converters) typically have high-accuracy problems. Due to the difficulty of accurately matching components on a semiconductor chip, it is often difficult to obtain conversion accuracy beyond 10 bits.

This new invention lowers the noise floor of the signal band, and achieves performances better that those predicted by the spectrum of the modulator output. Error correcting is particularly well suited to very low oversampling ratios. The correction is calculated and added in the digital domain so that this technique can be employed with existing architectures with only minor modifications.

Inventor(s): Yang, Woodward

Type of Offer: Licensing

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