A Parameterized VLSI Architecture for Binary Multipliers based on Optimal Partitioning and Redundancy Removal
A parameterized VLSI architecture for performing binary multiplication on signed and unsigned binary numbers or variable widths is the invention. The archictecture consists of two basic units. The first unit optimally paritions the computations that are involved in the multiplication of two binary numbers into a set of all possible distinct partial products. The second unit appropriately combines the distinct partial products generated by the first unit to obtain the desired product of the two b inary numbers under consideration. Any redundancy due to multiple appearances of a partial product is removed by computing the partial product only once. The partition size is optimized with respect to a partition parameter that is chosen to minimize desired computational complexity measures.Categories: Other
Type of Offer: Licensing
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