Fast and Accurate Simulation of High Speed VLSI Circuits (21004)

This invention makes it feasible to analyze high frequency VLSI circuit interconnects over multiple design iterations, because it analyzes circuits quickly and accurately. Commercially available Electronic Design Automation (EDA) Software performs quickly and well for certain applications, but either accuracy or speed suffers when applied to high frequency VLSI interconnects. The invention has analyzed one circuit in 10-25 seconds that the popular “SPICE” method could not analyze in several days.

Existing inventions rely upon so-called "AWE" (Asymptotic Waveform Evaluation) algorithms, which process information quickly but which lose accuracy when applied to high frequency VSLI circuits or to any application where harmonics are complex. Other methods, such as "Krylov Subspace" & "Complex Frequency Hopping," have been developed in recent years that are more accurate than AWE under the condition of complex harmonics. But solutions based upon these methods are extremely slow, which creates a problem when applied to multiple design iterations of high frequency VSLI circuitry. The invention relies upon a completely new algorithm that provides both high accuracy and fast processing when simulating high frequency VLSI circuit designs.

Current high-speed EDA solutions that simulate circuits cannot make use of parallel processors. The invention can run on parallel processors, which further speeds simulation runs when applied to VLSI circuits with multiple inputs. Today’s VSLI circuits often operate under high frequency conditions with multiple inputs, so the conditions under which the invention offers this added advantage are commonplace.


FIELD OF APPLICATION: The invention applies to circuit design of high frequency VLSI circuits, or to circuit design of any VLSI circuit with complex harmonics and the need to quickly process simulations. Advantages increase when the invention is applied to circuits with multiple inputs.

ADVANTAGES: Increased accuracy and reduced simulation run time.

STAGE OF DEVELOPMENT:

U. S. Patent No. 6,789,237 has issued, and Northwestern University seeks a licensing partner to commercialize this technology.

Inventor(s): Yehea I. Ismail

Type of Offer: Licensing



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