Method and Apparatus to Measure Path Slack Using On-Chip Programmable Capture Signal Generation
Background While timing-related failures are becoming increasingly common in nanometer technologies, and the importance of delay testing is becoming apparent, performing at-speed delay tests is still a challenge due to the limitations on the clock frequencies that can be provided by external test equipment. This drives the need to develop innovative test solutions that reduce dependence on expensive high-speed test equipment.
Invention Description The present invention removes the dependence on expensive high-speed test equipment for performing delay tests, by providing a technique to generate accurately controlled capture signal on the device under test itself. The capture clock frequency can be programmed as a part of the test vector, which allows higher flexibility during path selection for test. With the capability of having a programmable capture signal, the delay (and hence the slack) of any path being tested can be measured with considerable accuracy. This is useful not only for path delay characterization during post-silicon validation and debug but also for improving delay defect coverage by performing faster than at-speed capture.
Easy to implement, low area overhead Can be incorporated with the currently known ac-scan methods, namely Enhanced Scan, Launch on Shift Scan, and Launch on Capture scan Does not require programing or resetting the system PLL during test Can perform at-speed and faster than at-speed test Delay of any path measured by controlling the capture signal arrival time Capture frequency programmable as a part of the test vector Removes dependence on external test equipment for providing fast clocks Relaxes the need to select the longest path for testing Increases defect coverage, since delay defects of much smaller sizes can be detected
Market Potential/Applications Post-silicon timing characterization and debug Small delay defect detection
UT Researcher Jacob A. Abraham, Ph.D., Electrical and Computer Engineering, The University of Texas at Austin Rajeshwary Tayade, Electrical and Computer Engineering, The University of Texas at Austin
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