Multiple Via Structures for Reliability Improvement of Copper Damascene Interconnects

Background The semiconductor industry is actively developing copper (Cu) damascene structures for on-chip interconnects. Electromigration (EM) is a major reliability concern for copper damascene interconnects. Statistical studies have revealed multi-mode failures in the copper oxide dual damascene structures, with the early failures dominated by void formation at the via interface. Early failures are of primary concern since they dominate the lifetime of the chip as device scaling continues with increasing interconnect density. EM failure at the via is caused by flux divergence occurring at the via/line interface due to the presence of the diffusion barrier. In addition to EM, copper interconnects are also known to be prone to failure induced by stress-induced void formation. The nature of this failure mode is similar to EM except that the driving force is thermal stress instead of electrical current.

Currently, there is no known solution for reducing early failures due to EM or stress voiding in Cu damascene interconnects.

Invention Description This invention proposes a method to use multiple via structures to improve copper interconnect reliability. Recent electromigration experiments performed at the Laboratory for Interconnect and Packaging at The University of Texas at Austin showed that the proposed method is very effective in reducing early failures and improving electromigration reliability of the copper damascene interconnects. The method is expected to be effective for improving stress voiding reliability.

Benefits

The method improves EM reliability for Cu damascene interconnects by effectively reducing early failures and increasing electromigration lifetime. The multiple-via structure can be readily incorporated into the Cu dual damascene interconnect without extensive changes in the damascene process. The method is cost-effective and can be extended to future Cu interconnects with low k dielectrics and to improve stress voiding reliability.

Features

The multi-via structure can be readily incorporated into the Cu dual damascene interconnect without changes in the damascene process.

Market Potential/Applications Semiconductor industry: for reliability improvement of copper damascene interconnects

Development Stage Proof of concept

IP Status One U.S. patent issued: 6,919,639

UT Researcher Paul S. Ho, Ph.D., Mechanical Engineering, The University of Texas at Austin Ki-Don Lee, Mechanical Engineering, The University of Texas at Austin Ennis Ogawa, Ph.D., Microelectronics Research Center, The University of Texas at Austin Hideki Matsuhashi, Mechanical Engineering, The University of Texas at Austin

Type of Offer: Licensing



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