High Rate Digital Demodulator (GSC-13963)

Abstract:
NASA Goddard Space Flight Center¿s high-rate digital receiver performs demodulation and bit synchronization for quadrature PSK (QPSK) and binary PSK (BPSK) modulated signals. The parallel architecture of the HRDR provides the required functions by using decimated samples of the input signal and combining multiple data streams to reconstruct the full output signal. The radio frequency signal is digitized using an analogto- digital converter, and each symbol is sampled four times. These samples are then decimated by a factor of 16, allowing the chip to process the samples at one-fourth the data rate. The HRDR uses an innovative algorithm that accomplishes the discrete-time demodulation and synchronization of binary data in a parallel fashion. Signal processing rates are proven at 300 Mbps for BPSK-modulated data and 600 Mbps for QPSKmodulated data. Higher processing rates can likely be achieved by coupling the receiver with existing processors or using Feher QPSK and higher order QAM. The dual-ASIC circuitry is designed using standard CMOS technology instead of GaAs, allowing for a more compact design and lower power requirements. The cost to implement CMOS technology is also significantly lower than for other technologies, such as GaAs or analog circuitry.

Type of Offer: Licensing



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