High-Rate Parallel Digital Receiver ()

The design approach for the high-rate digital demodulator consisted of algorithmic development, software simulations, development of a hardware prototype in reprogrammable hardware, and finally, development of a single 800k gate CMOS ASIC. Two identical ASICs will be required in the digital receiver, one to perform in-phase channel processing and one to perform quadrature channel processing. The input signals to the digital demodulator ASICs are 8 parallel, 8 bit A/D samples that are demuxed to obtain 16 parallel 8-bit samples. Optionally, the samples can be Gray decoded as well as converted from unsigned numbers to signed numbers.

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