Parallel Subconvolution Filtering Architectures (NPO-30142)
Parallel implementations of large tap-length digital filters are complex digital designs and require large transistor count (real estate) to implement. The goal was to develop simple architectures to implement in parallel/vector processing form to reduce the processing rate required by the hardware and to be able to be extended to any length filter desired, with only linear increase in complexity. The improvement of these novel architectures is that they allow implementation of simple, very large scale integration with parallel processing for high-order filtering/correlation so that very high rate systems can be processed with lower rate hardware and relatively low complexity (low transistor count).
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