Broadband Clock Recovery Circuit Using YIG Oscillators
JHU/APL inventors have designed a Broadband Clock Recovery Circuit using YIG Oscillators with novel features compared to similar technologies currently circulating in this market. The fields of application for this invention include companies in Telecommunications and those involved in Test and Measurement Markets for universal broadband clock recovery for test sets.
Typical clock recovery circuits operate over a very narrow frequency range, centered on one of the SONET standard data rate frequencies, such as 155.52 MB/s, or some multiple of 2n of this rate. The decoding of data would require a specific clock recovery circuit designed for the particular data rate being decoded. While multirate recovery methods below 2.5 Gb/s exist, there are few broad band options above 2.5 GB/s. JHU/APL technology offers a broadband clock recovery at the high data rate speeds greater than 2 GB/s. This technology proves to be more consistent with the future plans for the optical network where there is a demand on the hardware to be transparent to the data on the network; a broadband recovery circuit is capable of handling multiple data rates/formats without the need for hardware modification. This new version of technology uses a high quality factor multi-octave oscillator for low phase noise as well as greater bandwidths using a YIG-based technique. Multiple circuits are not required for each bit rate and even nonstandard bit rates can be recovered.
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