Stack Data Cache Having a Stack Management Hardware with Internal and External Stack Pointers and Buffers for Handling Underflow and Overflow Stack

An efficient hardware cache manager controls the top-of-stack data underflow/overflow. A processor chip includes a processor, a stack buffer, and the invented cache management hardware. The processor chip communicates with a remove overflow stack through an address/data bus. The cache management hardware efficiently manages overflow and underflow to and from the processor chip in such a manner that less than 1% of the processor's time is spent managing the stack cache.

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