Hybrid Silicon Evanescent Devices

BACKGROUND: Conventional silicon photonic and optoelectronic devices are mostly built on silicon-on-insulator (SOI) wafers, where a buried SiO2 layer provides vertically optical confinement to maintain lightwave propagation. With increasing demand to replace electrons with light to be the information carrier for higher-speed data communication and lower power dissipation, optoelectronic devices also need to be placed in/among Complementary Metal Oxide Semiconductor (CMOS) devices fabricated on pure silicon wafers, such as in the case of memory/buffer devices. The most common guide-wave component, the “rib waveguide,” however, is unable to achieve on a pure silicon platform due to a lack of a lower cladding layer to prevent light from leaking into the entire substrate.

An amorphous material of low-index dielectrics, such as SiO2 or Si3N4 can be locally placed in a Si wafer. Crystalline Si, however, could not be grown or deposited on dielectrics easily. Local formation of SOI waveguides on pure silicon wafers, therefore, remains a challenge.

On the other hand, the buried oxide layer in the conventional SOI substrates serve as a natural thermal insulator with a ~10X lower thermal conductivity than that of Si. The heat generated in the top Si device layer is therefore unable to dissipate quickly through the substrate, making the device cooling very challenging.

DESCRIPTION: Researchers have developed a novel method to selectively create a buried SiO2 layer and subsequent SOI waveguide structure on bare silicon wafers, using the well-developed SIMOX process that is widely used to manufacture commercial SOI wafers. The SOI structure is selectively formed while implementing the same waveguiding function in the SOI region. And, unlike conventional SOI structures, the thermal resistance is dramatically reduced since top Si device layer and Si substrate are not completely isolated.

ADVANTAGES:

* Uses existing manufacturing methods
o Fully compatible with CMOS process
o Fully compatible with low-temperature, back-end process for integrating III-V chips on SOI regions

* Thermal resistance is dramatically reduced, when compared to conventional SOI structures
o Heat in the SiO2 region can be quickly extracted

* Manufacturing cost comparable to, or lower than, cost of commercial SOI wafers

APPLICATIONS:

* Recombinant cells producing vaccine virus

This technology is available for licensing.

REFERENCE: 2008-317

Type of Offer: Licensing



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