Complementary Field-Effect Transistor Logic Circuits for Wave Pipelining

This invention describes a novel CMOS digital circuit to improve wave-pipeline systems used in high speed digital systems. It uses complementary transmission gates and pull-up/pull-down transistors to create circuits tuned to provide substantially eq ual delays, high-quality ‘ones’ and ‘zeros’, and substantially equal rise and fall times, for every transition. Other advantages are:

1)Very high pipeline rates approaching physical speed limits, without much latency increase. 2)Minimizing clock loading and reducing clock distribution problems. 3)Using fewer registers and reducing the area overhead required by conventional pipelining.

This is applies to the areas of digital electronics and communication. It utilizes and builds upon wave- pipelining, increasing cost and time savings and efficiency and lowering complexity.

Categories: Instrumentation, General Engineering

Patents Issues: 5,528,177 5,701,094 5,796,624

Type of Offer: Licensing

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