Non-Uniform Cache Apparatus (NUCA), System, and Method

Background Traditional cache hierarchies are broken up into levels (L1, L2, L3, etc.) where each successive level is much larger and slower than the previous one. If a needed datum is not found in the fastest level, L1, in one to three cycles, the slower L2 is searched, taking 6 to 12 cycles, and so on. The increase in wire delays makes these discrete levels infeasible for caches integrated with the processor on the same silicon die, as, even within one level, the number of cycles will vary depending upon where in that level the data reside.

Invention Description The proposed NUCA system solves and exploits the problem by breaking a level of the cache down into many small banks, connected with a specialized network, that permit the close data to be accessed much faster than the farther data within the same level. The data are mapped into the cache to permit migration of data within one level; as a datum is referenced more often, it is moved progressively closer and closer to the processor, so that the most frequently accessed data are in the closer banks, and the least frequently accessed data are the farthest. This is accomplished by spreading cache sets across multiple banks.

Benefits

Improves computer system performance over conventional cache of the same area Flexible across range of applications Scales and improves with technology advancements Performance improves as it scales with cache size

Features

Mitigates the effect of slowing wires and provides high adaptivity Allows sophisticated allocation and sharing policies atop the basic NUCA structure Flattens memory hierarchy Stable organization Optimum cache size for each application

Market Potential/Applications The market is any high performance microprocessor vendor, particularly Intel, IBM, Sun, HP, and AMD. The workloads that would show benefits from this invention being incorporated onto the processors include server workloads (such as web serving, transaction processing, or databases), high-end consumer programs (such as games), or scientific/technical workloads (such as number crunching or engineering with CAD tools).

IP Status One U.S. patent issued: 6,965,969

UT Researcher Douglas C. Burger, Ph.D., Computer Sciences, The University of Texas at Austin Stephen W. Keckler, Ph.D., Computer Sciences, The University of Texas at Austin Changkyu Kim, Microprocessor Tech. Labs, The University of Texas at Austin

Type of Offer: Licensing



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