Three-dimensional Architecture for Solid State Radiation Detectors

Description A new architecture for solid-state radiation detectors has been developed that combines VLSI fabrication technology with tools and techniques from the growing field of micro-machining to create a three-dimensional array of electrodes which penetrates into the substrate bulk. As with planer-type detectors, a reverse-biased PIN diode serves as the basis for the design with a depleted intrinsic region providing a volume sensitive to ionizing radiation. The depth of the depleted region is determined by the cell pitch, not wafer thickness as with planar detectors, so the region that needs to be depleted is tens of microns thick instead of hundreds of microns. Since the voltage necessary to fully deplete the region is proportional to the square of its thickness, the depletion voltage for a 3D detector is a hundred times lower than for a planar detector. The fabrication steps to create the architecture can be varied to produce monolithic pixel detectors, bump-bonded detectors, and strip detectors, with or without on-chip driving electronics.

Patent Information U.S. Patent No. 5,889,313 issued March 30, 1999 U.S. Patent No. 6,204,087 issued March 20, 2001, continuation-in-part from U.S. Patent No. 5,889,313

Silicon Detectors with 3-D Electrode Arrays- Fabrication and Initial Test Results [PDF - 946KB]
Observation of Beta and X-Rays with 3-D Architecture Silicon Microstrip Sensors [PDF - 84KB]
Performance of 3-D Architecture Silicon Sensors [PDF - 184KB] Applications X-ray and ionizing radiation detectors in which high speed, extreme radiation hardness and high spatial resolution are important, mammography, medical imaging. Main Advantages High resolution Reduced charge collection distances Depletion voltages one-to-two orders of magnitude lowelower than for conventional planar technology strip and pixel detectors Collection times an order of magnitude faster than conventional detectors Increased resistance to radiation damage

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