Device for Generating Clock Signals for Asymmetric Comparison of Phase Errors

The invention relates to a device for generating clock signals, comprising a phase locked loop (100) including: - a controlled oscillator (101) capable of outputting a clock signal, - a plurality of phase comparators (102.1-102.4) capable of comparing a clock signal output by the controlled oscillator with a plurality of clock signal phases applied to the input of the phase locked loop, - means (110) for weighted summing of the output signals from the plurality of phase comparators such that one or more of the weighting coefficients applied to one of said output signals has an absolute value which overrides the absolute values of the other weighting coefficients applied to the other output signals, - means for filtering (112) the weighted sum of the output signals of the plurality of phase comparators, which are capable of outputting a control signal to the controlled oscillator.

WO 2,011,051,407


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