Method of High-Performance CMOS Design

Introduction Dynamic circuit families such as domino are commonly used in today’s highperformance microprocessors for obtaining timing goals that are not possible using static complimentary metal oxide semiconductor (CMOS) circuit. Their increased performance is due to reduced input capacitance, lower switching thresholds, and circuit implementations. However, dynamic circuits have notable disadvantages. Perhaps the main disadvantage is its increased noise sensitivity. Technology description Researchers at the UW have a developed a new technique called output prediction logic (OPL) that can be applied to a variety of inverting logic families to increase speed while retaining the attributes of the underlying family. OPL relies on the alternating nature of logical output values for inverting gates on a critical path. That is, for any critical path, the logical output values of the gates along that will be alternating ones and zeros. By correctly predicting exactly one half of the gate outputs, OPL obtains significant speedups (at least 2X) over the underlying logic families. OPL is the fastest known logic family. Since it is essentially a static logic family, it avoids many of the problems associated with dynamic logic. Business opportunity OPL is a new, much faster digital logic family that can be used to implement highspeed combinational logic in an integrated circuit. Applications that will benefit from the new logic family include the control blocks and datapaths in a microprocessor. Stage of development Initial data and working prototypes exist for this technology.

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