Scanning Probe Microscopy Based Diffusion of Dopant and Impurities

It is common to see devices shrink in size with time, especially electronic devices such as computers, cell phones, mobile music players, pagers, calculators etc. There are, however, some important working components in these devices that cannot be replaced by an alternate component but have to be designed in such a way that they fit the shrunk size. As the device size is reduced, conventional lithography techniques used for making these devices become hard to implement (in some cases useless). This technology describes an alternate method to produce a Field-Effect Transistor (FET) or other structures by using a scanning probe to define the various parts of a device. A novel technique called the scanning probe lithography is used instead of the conventional lithography to accomplish the manufacture of the size-reduced components.

With the device sizes shrinking throughout the world in all the fields this technology has broad applications. It can be used to build sub-micrometer devices.

Stage of Development
This technology is part of an active and ongoing research program and is available for developmental research support/licensing under either exclusive or non-exclusive terms.

Additional Info
*V.V. Zavyalov, J.S. McMurray, S.D. Stirling, C.C. Williams and H. Smith, �2D dopant and carrier profiles obtained by Scanning Capacitance Microscopy on an actively biased cross-sectioned MOSFET device,� J. Vac. Sci. Tech. B 18, 549 (2000).

Inventor(s): Jim Slinkman, Clayton Williams

Type of Offer: Licensing

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